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Tag: RISC-V architecture

  • Google uses RISC-V as its custom AI chip

    SiFive emerged as the world’s inaugural chip design manufacturer based on the RISC-V architecture, established in 2015. Over the years, SiFive has ascended to become a pivotal entity within the RISC-V ecosystem, distinguishing itself as a preferred source for the fabrication of miniature, cost-effective cores. However, the company has encountered some turbulence in its trajectory over the past two years, with reports last year of undergoing significant restructuring and substantial layoffs, primarily affecting engineers and personnel in product and sales departments.

    According to media sources, SiFive anticipates its revenue for 2024 to range between $240 million and $280 million, stemming from new contracts and licensing income. It is speculated that SiFive is poised to secure another significant contract with Google, which would involve providing core designs for the latter’s Tensor Processing Units (TPUs), thereby facilitating an upsurge in revenue.

    SiFive harbors high expectations for Google’s second-generation chips intended for Artificial Intelligence (AI) servers, although the specifics of the transaction remain undisclosed at this juncture, potentially earmarking a crucial revenue stream for SiFive in the future. It is conjectured that SiFive will grant Google a license to employ the Intelligence X390 core, tailored for AI and machine learning workloads.

    The Intelligence X390 boasts a single-core configuration, double the vector length, and dual vector Arithmetic Logic Units (ALUs) compared to its predecessor, the X280, thereby quadrupling vector computation capabilities and simultaneously enhancing sustained data bandwidth fourfold. With the incorporation of SiFive’s Vector Co-Processor Interface Extensions (VCIX), users are afforded the flexibility to append their vector instructions and/or accelerate hardware designs. Additional features include a 1024-bit Vector Length (VLEN), a 512-bit Data Length (DLEN), single/double vector ALUs, and VCIX (2048-bit output/1024-bit input).

    Google has previously utilized the Intelligence X280 as a coprocessor to orchestrate devices and furnish the Matrix Multiplication Units (MXUs) with requisite data for processing. Moreover, Google’s decision to continue incorporating SiFive’s designs in its next-generation AI systems is significantly motivated by the imperative of maintaining backward compatibility.

  • AMD is hiring RISC-V architecture engineers

    AMD’s Radeon Technology Group (RTG) is hiring a RISC-V CPU/GPU micro architect for its existing embedded RISC-V architecture team. This shows that AMD may develop solutions based on the RISC-V architecture for use in its related products in the future.

    Radeon Pro W6600X
    According to AMD’s job description, the main responsibilities of this position are:
    • Work with a team of architects developing innovative embedded RISC-V CPUs.
    • Identify complex technical problems, break them down, summarize multiple possible solutions, and help the team make advances in Performance, Power, and silicon Area (PPA).
    • Understand and improve existing and emerging graphics/compute paradigms and new APIs employing RISC-V processors.
    • Work with architects to understand bottlenecks and other problems where an embedded processor will improve the performance.
    • Propose innovative solutions that can be implemented in HW with the best PPA characteristics
    • Analyze CPU workloads and make recommendations for improvements.
    AMD expects the engineer to have RTL design experience, GPU experience, knowledge of branch predictors and register renaming, out-of-order execution, CPU principles of speculative execution, and RISC-V RV64 CPUs. The location of its work is Orlando, Florida, where a design team from Radeon Technology Group is located.

    In fact, AMD’s rivals Intel and Nvidia both have worked on the RISC-V architecture. Intel and RISC-V architecture chip design company SiFive have already cooperated to build their own RISC-V development platform Horse Creek using each other’s technology. Intel even intends to acquire the other party, and the related IP of SiFive can use Intel’s foundry service business (IFS) in the future. Some NVIDIA Turing architecture and Ampere architecture GPUs have a module called GSP (GPU System Processor) inside, based on the RISC-V architecture, it is used to take over GPU initialization and management tasks. In addition, the Bluefield series DPU also has a RISC-V accelerator.