AMD will increase the Zen 5 architecture CPU microcode capacity

In the recent release of AIDA 64 version v6.90, preliminary support for AMD’s Zen 5 architecture processor has been initiated, signifying that the Ryzen 8000 series has taken another stride toward the consumer’s reach. Earlier reports have suggested that AMD plans to unveil its novel Zen 5 architecture in 2024, with corresponding products possibly launching in the first half of the year, or even as early as the first quarter.

According to Phoronix, a recent discovery of a new Linux patch indicates that the microcode capacity limit of AMD’s next-generation processors will swell from 12KB to 32KB. This intimates that AMD may support more complex instructions on the upcoming Zen 5 architecture and subsequent products, reserve space for adding new features post-launch, or pursue a more comprehensive microcode update.

In a statement, AMD conveyed that the microcode for future processors will exceed the current limitation of three 4K pages. Although the microcode for Zen 5 architecture processors may not necessarily be 2.6 times or more than that of Zen 4 architecture processors, the fact remains that it has expanded, with AMD leaving ample room for expansion.

The microcode of a processor delineates how it operates, serving largely as a manual instructing the processor on how to execute each machine code instruction: breaking down high-level machine code instructions into simpler, hardware-level instructions that the processor can execute. Generally, the more complex the instruction set, the more complex the microcode. The processor’s microcode can usually be updated, allowing developers to rectify errors or security vulnerabilities post-product deployment. If AMD aims to implement complex new instruction set extensions in its products, an unavoidable necessity would be the enlargement of its microcode size.

Another scenario could be that AMD seeks to incorporate new features or functionalities, or intends to do so without necessitating the complete redesign of the processor.