Memory Revolution: 1000-Layer 3D NAND by 2031
The volume of data generated globally each day is colossal, stored in high-capacity servers and data centers via HDDs and SSDs. However, SSDs, with their superior read/write speeds, lower energy consumption, and compact device sizes, are gradually supplanting HDDs. One reason for the reduction in the cost per unit of SSDs is attributed to stacking an increased number of layers in the storage cells.
According to Xtech Nikkei, Kioxia’s Chief Technology Officer, Hidefumi Miyajima, announced at the 71st Spring Meeting of the Applied Physics Association held at Tokyo City University, plans to commence mass production of 3D NAND flash memory chips with over 1000 layers by 2031.
Enhancing the number of active layers within 3D NAND devices is currently the most effective strategy to augment flash memory recording density. Consequently, all 3D NAND manufacturers aim to achieve this objective approximately every 1.5 to 2 years through new process technology nodes. However, each new process technology node introduces challenges. Due to the need for stacking more layers on the 3D NAND flash memory, it necessitates the reduction of storage cell sizes both horizontally and vertically, incorporating new materials, which presents considerable research and development difficulties for manufacturers.
Kioxia’s latest achievement is the launch of its 8th generation BiCS 3D NAND flash memory, which boasts 218 layers. In collaboration with Western Digital, Kioxia developed the CBA (CMOS directly Bonded to Array) technology, where each CMOS wafer and cell array wafer is manufactured separately under optimal conditions and then bonded together. This process enhances bit density and speeds up the NAND I/O interface significantly. Through innovative lateral shrinkage technology, bit density has increased by more than 50%, and the NAND I/O interface speed has surpassed 3.2Gb/s, marking a 60% improvement over the previous generation.
Kioxia is expected to continue its current technological trajectory to develop a 3D NAND flash memory chip with 1000 layers.
