AMD showcases 3D Chiplet architecture: increases the L3 buffer in the CCD to 96MB

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AMD has been practicing MCM multi-chip packaging for many years, and they have actually cooperated with TSMC in 3D packaging. At the end of today’s  COMPUTEX 2021 conference, AMD CEO Dr. Lisa Su announced an exciting technology – 3D Vertical Cache.

AMD combines Chiplet packaging technology with chip stacking technology to create a 3D Chiplet architecture, and the 3D vertical cache is the first practice of this technology.

AMD packed a 64MB 7nm SRAM on the CCD of the existing Zen 3 architecture Ryzen 5000 processor. This SRAM is directly stacked on the CCD chip so that the L3 cache capacity of each CCD can be increased from 32MB to 96MB.

Due to the advanced technology, this SRAM is very thin, with structural silicon added on both sides, and the combined chip makes a seamless surface, which is exactly the same as the current Ryzen 5000 processor in appearance.

This is the prototype design of the Ryzen 9 5900X processor using 3D stacking technology. On the left chip, there is a 6mm*6mm square SRAM combined with CCD, which is processed in a 12-core or 16-core Ryzen 9 with dual CCDs. There is a total of 192MB of L3 cache on the device.

After adding the 3D vertical cache, the average frame rate of the 12-core Zen 3 Ryzen processor in “Gears of War 5” at the same frequency has increased by 12%. AMD said that it would prepare to produce some high-end products with 3D chiplet before the end of this year, but did not specify what it is, but it may be the Ryzen 5000 XT series processors.

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