SK hynix has developed DDR5 DRAM CXL memory
SK hynix announced that it has developed the first CXL memory sample based on DDR5 DRAM, which will accelerate the pace of seizing the market for next-generation memory solutions, with mass production planned for 2023. The CXL memory of SK hynix adopts the shape of EDSFF E3.S specification, supports PCIe 5.0 x8 channels, is equipped with a CXL controller, and uses DDR5 standard DRAM.
As an open interconnection protocol, PCIe-based CXL has higher bandwidth and enables high-speed and efficient interconnection between CPU and GPU, FPGA, or other accelerators, which meets the requirements of today’s high-performance heterogeneous computing, and provides higher bandwidth and better memory consistency. SK hynix has been actively involved in the CXL Alliance since its inception, leading the development of CXL memory.
SK hynix said that the DDR5 DRAM CXL memory is a 96GB product, which adopts the latest technology node 1anm DDR5 24Gb DRAM, and can be expanded through flexible bandwidth configuration and cost-effective capacity.
SK hynix also developed the Heterogeneous Memory Software Development Kit (HMSDK) exclusively for CXL memory devices which will be equipped with system performance enhancement functions and monitoring functions applicable in various drive environments, which will help users to use SK hynix’s CXL memory more efficiently.
SK hynix is planning to exhibit the product in upcoming events, beginning with Flash Memory Summit in early August, Intel Innovation at the end of September, and Open Compute Project (OCP) Global Summit in October, while scheduling to demonstrate a demo with HMSDK as well.
