Intel aims to launch Arrow Lake-S in the latter half of 2024

Intel, with the release of Arrow Lake-S next year, is set to introduce its next-generation LGA 1851 platform. Rumors suggest that this new platform will support three product generations, possibly encompassing Arrow Lake-S, Arrow Lake Refresh, and Panther Lake-S (alternatively referred to as Nova Lake-S).

Recent revelations from Twitter user @momomo_us indicate that Intel aims to launch Arrow Lake-S in the latter half of 2024, with the corresponding LGA 1851 platform remaining in use until 2026. This aligns with prior speculations regarding support for three product generations. Diverging from the existing LGA 1700 platform, insider reports suggest that the LGA 1851 will make a complete transition to DDR5 memory, foregoing DDR4 compatibility— a development many have anticipated.

The LGA 1851 socket boasts 1851 contact points, an 8.9% increment compared to the currently utilized LGA 1700 socket. This surge in contact points is notably more modest than the 41.7% increase observed when transitioning from LGA 1200 to LGA 1700. Current data on the LGA 1851 socket suggests that the Z-height remains constant, with no alterations in the distance between the top of the circuit board and the Integrated Heat Spreader (IHS). Despite the increased pin count, the physical dimensions remain congruent with Alder Lake and Raptor Lake’s LGA 1700 socket, adhering to a 45 × 37.5 mm specification. However, the maximum dynamic load has nearly doubled, rising from 489.5 N to 923 N, implying enhanced safety during transportation, vibrations, and shocks. Furthermore, with the Z-height retained, existing fasteners may very well continue to be compatible.

Arrow Lake-S will persevere with its Tile design, where diverse modules, crafted using varied manufacturing nodes, are stacked and interconnected using EMIB technology, further encapsulated with Foveros packaging techniques. Beyond the L2 and L3 cache, there’s speculation that its GPU module will feature an exclusive cache, and the L2 cache for every P-Core will augment to 3MB. Additionally, there are indications that the Intel 20A process intended for Arrow Lake-S might face delays, potentially prompting Intel to pivot to TSMC’s 3nm process.