AMD EPYC “Siena” 8004 series has at least 6 models

Several months ago, reports surfaced that AMD’s EPYC 8004 series server processor, codenamed “Siena,” had received validation from SATA-IO. Targeted at single-socket, low-end servers, this processor series focuses on optimization for density and performance-to-power ratio, catering to the edge and telecommunication sectors. It aims to achieve enhanced energy efficiency and is suitable for low-power servers with reduced total cost of ownership (TCO).

Recent revelations from Twitter user @momomo_us indicate that the EPYC 8004 series server processor is poised for release, with an anticipated launch date falling sometime later this year to early next year. It will be built on the Zen 4 architecture core, offering at least six models—namely, 8024P, 8124P, 8224P, 8324P, 8434P, and 8534P—corresponding to 8, 16, 24, 32, 48, and 64 cores. The L3 cache will range between 32MB to 128MB, with operating frequencies from 2.2 GHz to 2.55 GHz, and power consumption varying from 90W to 200W.

Presently, the known EPYC 9004 series server processors, codenamed Genoa, Genoa-X, and Bergamo, utilize a larger SP5 socket, with the highest TDP standing at 400W. In contrast, the Siena AMD EPYC 8004 series will transition to the SP6 socket. It is understood that the SP6 socket closely resembles the commonly used SP3 socket, retaining the same dimensions (58.5 x 75.4 mm), although it features a distinct LGA packaging and consists of 4844 pins. In both size (76.0 x 80.0 mm) and pin count (6069), it is noticeably smaller and fewer than the SP5 socket.

Furthermore, the processors using the SP6 socket, corresponding to Zen 4 and Zen 4c architectures, have seen reductions in the number of memory, PCIe, and CXL channels. Rumors suggest that the EPYC 8004 series server processors support 6-channel DDR5-4800 memory and have 96 PCIe 5.0 lanes, CXL v1.1+ lanes, and 8 PCIe 3.0 lanes.