TSMC Unveils A16: Powering the Future of AI

Recently, Taiwan Semiconductor Manufacturing Company (TSMC) held its 2024 North American Technology Forum, unveiling its latest advancements in process technology, advanced packaging, and 3D Integrated Circuits (3D IC). These sophisticated semiconductor technologies are poised to propel the next wave of innovation in artificial intelligence (AI).

TSMC announced for the first time the A16 process technology, which integrates nanosheet transistors and backside power delivery solutions to significantly enhance logic density and energy efficiency. Additionally, TSMC introduced the System on Wafer (TSMC-SoW) technology, offering revolutionary wafer-level performance advantages to meet the future demands of hyperscale data centers for AI applications. The newly revealed technologies include:

• A16 Process Technology: The A16, incorporating the Super Power Rail architecture and nanosheet transistors, is expected to enter mass production in 2026. The Super Power Rail architecture, also known as backside power delivery, frees up layout space on the front side to increase logic density and performance, making it suitable for high-performance computing (HPC) products with complex signaling and dense power networks. Compared to the N2P process, the A16 offers a speed increase of 8-10% at the same operating voltage, or a 15-20% reduction in power consumption at the same speed, while also increasing density by 1.1 times.
• NanoFlex Technology: The upcoming N2 process will be paired with NanoFlex technology, providing chip designers with flexible standard components. These fundamental building modules allow for area savings and higher power efficiency with shorter components, while taller components maximize performance. Designers can optimize the combination of high and low components within the same design block, adjusting the design to achieve an optimal balance between power consumption, performance, and area.
• N4C Process Technology: Extending from the N4P technology, the N4C reduces transistor costs by 8.5% and lowers barriers to entry, with mass production anticipated in 2025. Compatible with N4P, customers can easily transition to N4C, benefiting from reduced transistor sizes and improved yields, providing a cost-effective choice for value-focused products.
• System-level Wafer (TSMC-SoW): TSMC’s CoWoS advanced packaging is a key driver of the AI revolution, allowing customers to place more processor cores and high-bandwidth memory (HBM) side by side on a single interposer. TSMC’s System on Integrated Chips (SoIC) has become a leading solution for 3D chip stacking, with increasing adoption of CoWoS in conjunction with SoIC and other components for ultimate System in Package (SiP) integration.
• Silicon Photonics Integration: TSMC is developing the Compact Universal Photonics Engine (COUPE) technology, which uses SoIC-X chip stacking to layer electronic bare dies on top of photonic bare dies. Compared to traditional stacking methods, this approach provides the lowest resistance and highest energy efficiency between interfaces. TSMC expects to complete the COUPE validation with small form-factor pluggable connectors in 2025 and integrate it with CoWoS advanced packaging into Co-Packaged Optics (CPO) by 2026, incorporating optical connections directly into the packaging.
• Advanced Packaging for Automotive: Following the launch of the N3AE process in 2023 to support automotive clients, TSMC continues to meet the growing demand for higher computing capabilities in automotive applications while adhering to automotive safety and quality standards. TSMC is developing the InFO-oS and CoWoS-R solutions to support advanced driver assistance systems (ADAS), vehicle control, and central computing applications, with completion of AEC-Q100 Level 2 qualification expected by the fourth quarter of 2025.

TSMC affirms its commitment to providing clients with the most comprehensive technology offerings, from cutting-edge manufacturing processes to the broadest array of advanced packaging solutions, to realize the vision for artificial intelligence.