PCI-SIG announces version 0.5 of PCIe 7.0 specification

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At the 2022 PCI-SIG Developers Conference, PCI-SIG commemorated its 30th anniversary and unveiled the forthcoming PCIe 7.0 specification, scheduled to be released to its members in 2025. Recently, PCI-SIG announced the launch of the 0.5 version of the PCIe 7.0 specification for member review. This marks the official first draft of the PCIe 7.0 specification, incorporating all feedback received from members since the release of the 0.3 version in June 2023.

Compared to the PCIe 6.0 specification, the data transfer rate of PCIe 7.0 will double once again, reaching 128 GT/s—a significant leap from PCIe 6.0’s 64 GT/s and PCIe 5.0’s 32 GT/s. A PCIe 7.0 x16 channel will be capable of supporting 512 GB/s, utilizing four-level Pulse Amplitude Modulation (PAM4) signaling, 1b/1b flit mode encoding, and Forward Error Correction (FEC)—all features carried over from the PCIe 6.0 specification.

Furthermore, the PCIe 7.0 specification will focus on enhancing channel parameters and coverage range, continuing to achieve goals of low latency and high reliability, improving power efficiency, and maintaining backward compatibility with all previous generations of PCIe technology. PCI-SIG envisions the PCIe 7.0 specification as a scalable interconnect solution for data-intensive markets such as 800G Ethernet, artificial intelligence/machine learning, hyperscale data centers, high-performance computing (HPC), quantum computing, and cloud services.

Like other specifications designed by PCI-SIG, each PCI Express specification goes through five key stages:

  • 0.3 version: Concept. This draft outlines the objectives to be achieved and the methods for achieving them.
  • 0.5 version: First draft. This version must fully address the goals set in the 0.3 draft, including all architectural aspects and requirements, and incorporate feedback from stakeholders, allowing PCI-SIG members to add features to the specification under development.
  • 0.7 version: Complete draft. This version must have a full set of functional requirements and method definitions, as no new features can be added after this stage. Additionally, the electrical specifications must have been validated using test chips. At this point, PCI-SIG members can propose different implementations of the new interface.
  • 0.9 version: Final draft. At this stage, PCI-SIG members are conducting an internal review of the technology to ensure intellectual property and patent compliance, with no functional modifications allowed.
  • 1.0 version: Final version. From this version onwards, all changes and enhancements must be made through formal errata documents and Engineering Change Notices (ECN).

It is understood that the PCIe 7.0 specification will require shorter PCIe traces, thereby reducing the distance between root devices and endpoint devices. Currently, implementing PCIe 5.0 designs necessitates thicker PCBs and higher-quality materials, implying increased costs. It remains unclear how PCIe 7.0 will address these considerations.

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