Samsung announced the latest Back Side Power Delivery Network research results
Last year at SEDEX 2022, Samsung introduced a technology referred to as “BSPDN” (Back Side Power Delivery Network), slated for implementation in future 2nm chips. It is claimed that the application of BSPDN in the 2nm process, coupled with back-end interconnect design and logic optimization, can resolve the front-end wiring congestion caused by FSPDN, enhancing performance by 44% and improving power efficiency by 30%.
According to The Elec, Samsung recently divulged its latest research findings on BSPDN at a VLSI symposium. The tech giant also elucidated how BSPDN can amplify the utilization of electrical energy, and overcome interconnect bottlenecks and cost issues, as well as the technical challenges faced by BSPDN. For instance, tensile stress might lead to the detachment of the metal layer from TSV (Through-Silicon Via) electrodes, a problem that may be rectified by either reducing the height of TSV or broadening its width.
Samsung articulated that in comparison to FSPDN (Front-Side Power Distribution Network), BSPDN has reduced the area by 14.8%. Specifically, Samsung achieved a respective area reduction of 10.6% and 19% in two Arm circuits, as well as a shortened wiring length of 9.2%. The benefit of a diminished area is the creation of more space for additional transistors, thereby augmenting overall performance. The curtailment in wiring length can minimize resistance, allowing a greater current to pass through and thus diminishing power loss, thereby enhancing power transmission. The novel BSPDN method has yet to be adopted by Samsung’s foundry services, and although Samsung is not the first to develop back-side power technology, it is the first to publicly reveal innovative method results.
Intel also recently detailed its developmental PowerVia technology, planned for introduction in the Intel 20A process node. This is Intel’s proprietary, industry-first back-side power distribution network, which optimizes signal transmission by eradicating the need for front-side power wiring in the wafer. According to Intel, back-side powering enables an exceptionally direct path for transistor powering, reducing signal interference and power consumption, optimizing platform voltage by 30%. On the other hand, back-side powering resolves the interconnect bottleneck caused by the continual shrinking of transistor size, achieving a 6% frequency gain and utilization of over 90% in standard cells.
