TSMC’s N3 series process cannot increase the SRAM density

In the bygone month, TSMC unfolded the blueprint of its cutting-edge semiconductor manufacturing techniques, incorporating a myriad of processes at 3nm and 2nm nodes. This year, TSMC is set to launch an augmented N3E process, offering superior cost efficiency and heightened economic returns. The enterprise aims to supply a broader product assortment at the 3nm node, inclusive of N3P, N3X, and N3AE, thereby catering to a multitude of client requisites.

It has been noted by WikiChip that recent disclosures reveal a little distinction between SRAM units on TSMC’s 3nm node and the 5nm node. Though TSMC had initially suggested that the new node offers a 20% boost in SRAM unit density compared to its predecessor, recent updates suggest the difference to be rather insignificant. Past reports indicated that TSMC confronted issues with the rate of SRAM unit reduction at the 3nm node.

In the enhanced N3E process, TSMC has incorporated the SAC solution, originally adopted by Intel during its 22nm phase in 2011, thereby improving yield rates. Nevertheless, regardless of the improvements in the N3E process, the density of SRAM units remains scarcely changed. This has led TSMC to focus on enhancements in logic density and manufacturing steps when discussing advancements in the new nodes, deliberately sidestepping this issue.

Modern processors possess a substantial area and transistor count occupied by SRAM. Without noticeable upgrades, the benefits of transitioning chips to new nodes become less apparent. Particularly considering the steep rise in the cost of TSMC’s 3nm node, leading numerous chip companies to adopt a wait-and-see attitude, avoiding placing orders. In fact, the reduction in SRAM size is no longer correlated with increases in logic density, a state of affairs that has persisted for some time, and presently, the two bear little association.