TSMC Introduces Its CFET Transistor Technology
At the recent ITF World 2023 held in Antwerp, Belgium, Intel outlined the latest developments in several key areas, among them the forthcoming adoption of the stacked CFET transistor architecture. As a current leader in semiconductor manufacturing technology, TSMC also elucidated its prospective GAAFET and CFET transistor technologies at the 2023 European Technology Symposium.
According to AnandTech, TSMC has divulged that its CFET transistors have reached the laboratory stage, undergoing testing for performance, efficiency, and density. In comparison with GAAFET, these aspects promise to hold superior benefits. However, the realization of CFETs necessitates additional fabrication steps to ensure the chip operates as intended. CFET transistors involve stacking n and p MOS devices atop each other, requiring the use of high-precision, high-power High-NA EUV lithography for manufacture.
TSMC is engaged in the study of various transistor design types, and research projects that demand extensive time, and the CFET technology could potentially emerge as one of the most probable candidates in the future. However, it can’t currently be stated that it has surpassed Nanosheet, and CFET transistors require the integration of novel materials into the manufacturing process, leading to larger investments for the corresponding process node. The only certainty is that TSMC will introduce GAAFET transistor technology commencing from the 2nm process.
TSMC has utilized FinFET transistors for a decade, evolving through five generations of technology. By precedent, GAAFET transistors should also span multiple product generations, whereas the journey to mass production for CFET transistors remains a distant prospect.