Tokyo Electron has developed a new 3D NAND flash for stacking more than 400 layers
Tokyo Electron (TEL) has announced the advent of an innovative through-hole etching technique developed and fabricated at its plasma etching system site, intended for the stacking of over 400 layers of advanced 3D NAND flash memory. The development team, for the first time, introduced dielectric etching in a low-temperature regime, thereby orchestrating a system with an extraordinarily high etch rate.
This avant-garde technology not only accomplishes a high-aspect-ratio etch of 10 micrometers deep within a mere 33 minutes, reducing the time factor but also yields a conspicuously geometrical etching structure, which potentially facilitates the production of higher-capacity 3D NAND flash memory chips.
Tokyo Electron has provided accompanying images post-etching, showcasing the fruits of their labor. Included are SEM cross-section images displaying the pattern of through-holes post-etching, FIB-cut images of the bottom of the hole, and a case of Tokyo Electron’s 3D NAND flash memory chips.
Tokyo Electron has also issued a proclamation stating that the team responsible for developing this technology will present their most recent research findings at the Symposium on VLSI Technology and Circuits held in Kyoto from June 11th to 16th, 2023. This prestigious gathering is one of the most renowned international semiconductor research conferences. Capitalizing on this opportunity, Tokyo Electron will demonstrate its contribution towards semiconductor technology innovation and the global environment.
Marking Tokyo Electron’s 60th anniversary this year, the company views this as a pivotal point of transformation to meet future challenges and continue contributing to societal advancement.
