Latency Slayer: Zen 6 Ryzen CPUs Coil Up with Next-Gen Chip Tech

Last year, an AMD engineer leaked information about the Zen 6 architecture, revealing that its internal codename is ‘Morpheus’. This architecture is expected to be manufactured using the 2nm process technology. If AMD continues its partnership with TSMC, given their semiconductor process advancements, processors based on the Zen 6 architecture could debut as early as late 2025 to early 2026.

Recently, online sources have brought forward new details about the Zen 6 architecture, indicating that the Ryzen processors built on this architecture are codenamed ‘Medusa’ and will feature advanced 2.5D interconnect technology with higher bandwidth. The adoption of this innovative 2.5D chip design interconnect technology will likely expedite communication between the CCD (Core Complex Die) and IOD (I/O Die), reducing latency and enhancing performance.

The 2.5D interconnect is not an unfamiliar concept; it’s currently showcased in the RDNA 3 architecture’s Navi 31/32 chips, which consist of GCD (Graphics Compute Die) and MCD (Multi-Cache I/O Die), utilizing two distinct manufacturing processes. For Zen 6 architecture Ryzen processors, AMD is likely to continue with the dual CCD paired with a single IOD design, where the latter may be enlarged to incorporate additional new technologies.

Moreover, AMD does not currently plan to stack the IOD on top of the CCD due to the high manufacturing costs. However, future designs might explore such an arrangement, akin to the Zen 3/4 architecture Ryzen 5000/7000X3D series desktop processors that incorporated 3D Vertical Cache (3D V-Cache) technology.