Intel Arrow Lake-S will support instruction sets such as AVX-VNNI

While Arrow Lake’s debut remains some distance away, Intel has preemptively fortified its ISV ecosystem to brace for the emergent technologies of the upcoming microarchitecture. In the instruction set reference guide released this July, it was revealed that Arrow Lake would support a gamut of instruction sets, encompassing AVX-VNNI-INT16, SHA512, SM3, and SM4.

Recently, astute netizens discerned a disparity in the instruction sets supported by Arrow Lake chips for desktop and mobile platforms. Notably, the Intel Arrow Lake-S for desktops is slated to support a more expansive repertoire of instruction sets. Typically, server processors encompassing instruction sets not present in client processors are commonplace, yet such a divergence in Arrow Lake is a rarer occurrence.

It is understood that the Arrow Lake-S, compatible with the LGA 1851 socket, will support the aforementioned AVX-VNNI-INT16, SHA512, SM3, and SM4 instruction sets and is also poised to incorporate the LBR event logging feature. Contrarily, for mobile platform chips, Intel has abstained from proffering these supports. The precise rationale remains shrouded in ambiguity, though speculation suggests that the ultra-low power consumption x86 cores of mobile platform chips may have influenced Intel’s decision to forgo enabling these functionalities on computational modules.

AVX-VNNI-INT16, with its emphasis on AI workloads, accelerates convolutional neural networks and deep learning tasks, rendering it invaluable for generative AI applications. As for SHA512, SM3, and SM4, their inception aims to bolster security and cryptographic prowess. SHA512, a widely adopted cryptographic hash function, ensures enhanced data integrity and secure data transmission.