Intel and TSMC reveal progress on next-generation CFET transistors

As reported by eeNewEurope, Intel and TSMC (Taiwan Semiconductor Manufacturing Company) are poised to unveil advancements in the next-generation CFET (Complementary Field-Effect Transistor) at IEDM 2023. The imminent stacked CFET architecture is slated to supersede the GAA (Gate-All-Round), heralding a new era in transistor design.

The CFET transistor amalgamates both n-type and p-type MOS devices, stacked in synergy, demanding the precision and prowess of high-NA EUV lithography for its fabrication. This paradigm was initially propounded by the IMEC institute in 2018. Although the nascent exploratory endeavors were primarily academic, both Intel and TSMC have audaciously ventured into this domain, fervently pursuing research on the succeeding transistor architecture.

Intel has already sculpted a monolithic 3D CFET, meticulously arraying three n-FET nanosheets atop a triad of p-FET nanosheets, maintaining a vertical interstice of 30nm. Intel’s discourse is titled, “Demonstration of a Stacked CMOS Inverter with Power Vias and Direct Backside Component Contacts with a 60nm Gate Pitch,” delineating a functional inverter test circuit employing CFET at a 60nm gate pitch. This avant-garde design incorporates vertical stratified dual power source drains, and dual-metal gate stacks, and synergizes with Intel’s PowerVia backside power supply technology.

TSMC, on the other hand, will elucidate its pragmatic approach to CFET, meticulously tailored for the fabrication of logic chips, boasting a 48nm gate pitch. TSMC’s blueprint accentuates a stratified n-type nanosheet transistor juxtaposed above a p-type transistor, engendering an astonishing six orders of magnitude in its on/off current ratio. TSMC has vouched for the durability of its design, with over 90% of the transistors withstanding rigorous testing. However, TSMC concedes that to harness the full potential of CFET technology, a plethora of functionalities awaits assimilation, with ongoing endeavors being pivotal to this ambition.

The CFET technology heralds a conspicuous paradigm shift in transistor design, sanctioning the vertical stacking of two transistors within the precincts of a singular transistor’s footprint, thereby augmenting transistor density on chips. Such an architectural feat not only proffers solutions for enhanced spatial utilization but also fosters a more streamlined CMOS logic circuitry layout, bolstering design efficiency. The inherent structure of CFET mitigates parasitic effects, paving the way for heightened performance and power efficiency. Furthermore, its integration with nascent technologies like backside power supply can attenuate the intricacies of fabrication processes.