TSMC started the technology research and development of 1.4nm process

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Judging from reports in the past period, TSMC has made good progress in the development of 3nm and 2nm processes. This time TSMC President Wei confirmed that the N2 process node will use Gate-all-around FETs (GAAFET) transistors as expected. The manufacturing process still relies on extreme ultraviolet (EUV) lithography and is expected to be ready for risk production in late 2024 and into high-volume production in late 2025.

TSMC chip supply shortage
With the breakthrough in the development of the 2nm process, TSMC has begun to consider advancing the next process node. It is rumored that the 1.4nm-level technology may be officially announced at the technical seminar held in June, and some technical details may be announced at that time. According to Business Korea, TSMC intends to reassign its N3 process node team in June to form an R&D team for the 1.4nm-class manufacturing process.

It is unclear which process Intel and Samsung will use to benchmark with TSMC’s 1.4nm-level process. According to the technology roadmap of the process technology announced by Intel last year, only Intel 18A (1.8nm-level) is currently arranged. Intel plans to introduce two breakthrough technologies, RibbonFET and PowerVia, at the Intel 20A process node. It also recently vowed to launch the Intel 18A (1.8nm level) with an improved RibbonFET in late 2024, ahead of TSMC’s 2nm process to achieve a performance-per-watt lead.

Many people in the industry are skeptical of the foundry’s manufacturing process plan, worrying that there will be more unpredictable obstacles in research and development, which will lead to delays in mass production time or unsatisfactory yields. As chip sizes get smaller and process technology barriers get higher, circuits must be drawn more precisely, and production management becomes more difficult.

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