Taiwan Semiconductor Manufacturing Company (TSMC) announced the launch of the N4P process, which is an enhanced process based on the current 5nm process node with a focus on performance. TSMC said that with N5, N4, N3, and the latest N4P, TSMC customers can have very flexible process options in terms of performance, area, cost, and power consumption of their products.
The N4P process is the third major improvement of TSMC’s 5nm process node. The performance is 11% higher than the earliest N5 process and 6% higher than the N4 process. Compared with the N5 process, there is a 22% increase in energy efficiency and a 6% increase in transistor density. In the N4P process, TSMC reduces the complexity of the process and shortens the cycle by reducing the number of masks. With the help of TSMC and its Open Innovation Platform partners, the first products based on the N4P process may be taped out in the second half of 2022.
The N4P process, like the previous N4 process, provides more PPA (power, performance, area) advantages, but maintains the same design rules, design infrastructure, SPICE simulation program, and IP. Products based on the original N5 process can be easily moved to the N4P process, which can better maximize customer investment and provide faster and more energy-saving products. Although the N4P process is not a revolutionary manufacturing process, for existing TSMC customers, it is likely to be used in some mainstream products in the next few years.
TSMC believes that the combination of advanced logic semiconductor technologies has been strengthened through the N4P process, and each technology provided will have a unique combination of performance, energy efficiency, and cost. The optimized N4P process may further provide an enhanced advanced technology platform for HPC and mobile products.