The official programming guide from AMD has confirmed the upcoming release of a hybrid architecture designed APU

Recently, there were reports that an unannounced processor from AMD appeared in the MilkyWay@Home database, which showed that it had 6 cores and 12 threads, including 2 performance cores and 4 efficiency cores. The new chip features a design similar to that of Big.Little, and some experts believe it is AMD’s APU codenamed “Phoenix 2”. The performance cores are equipped with 2MB of L2 cache and 4MB of L3 cache, while the efficiency cores have 4MB of L2 cache and 4MB of L3 cache. Additionally, it integrates a graphics core based on the RDNA 3 architecture, with 512 stream processors and support for DDR5/LPDDR5X memory.

Recently, Twitter user @InstLatX64 discovered that an official programming guide from AMD clearly marked the two types of cores in the Family 19h Model 70h series, commonly known as “big-little”. The performance cores are labeled as 0h and the efficiency cores as 1h, corresponding to the Zen 4 architecture and Zen 4c architecture, respectively.

AMD has pointed out that the two types of cores have different feature sets, so software developers should optimize their designs accordingly. However, to date, AMD has only confirmed the use of Zen 4c architecture cores in its Bergamo EPYC processor.

Clearly, a hybrid architecture design APU would enhance AMD’s competitiveness in the mobile market and better compete against Intel’s Alder Lake and Raptor Lake products. The combination of 2 performance cores and 4 efficiency cores should be aimed at ultra-low-power ultrabooks.

In any case, according to AMD’s plans, this hybrid architecture design APU will be launched this year and will soon meet consumers.