Samsung will use BSPDN to build 2nm chips
Samsung has introduced a new GAAFET full-surround gate transistor architecture on the 3nm process, which has been successfully mass-produced. According to the semiconductor process roadmap announced by Samsung, it plans to start mass production of the 2nm process in 2025, while the more advanced 1.4nm process is expected to be mass-produced in 2027.
Image: IMEC
According to The Elec, Samsung plans to use a technology called “BSPDN” (back-side power delivery network) for use on 2nm chips. Samsung researcher Park Byung-jae introduced the relevant situation of BSPDN at SEDEX 2022, saying that the technology has changed from the past high-k metal gate planar to FinFET, then to MBCFET, and then to BSPDN. I believe that many people are very familiar with FinFET. In the past, it was called a 3D transistor, which is the key technology of the 10nm-level process, and now Samsung has turned to GAAFET.
In the future, with the help of the small chip design scheme, the same process can no longer be applied to a single chip, but various chip modules manufactured by different processes from different foundries can be connected, also known as 3D-SOC. BSPDN can be understood as an evolution of chiplet design, combining logic circuits and memory modules. Unlike existing solutions, the front side will have logic functions, while the back side will be used for the power supply or signal routing.
In fact, BSPDN is not the first time. It was presented as a concept at the 2019 IMEC workshop and referenced in a 2021 IEDM paper. It is said that the application of BSPDN in the 2nm process, through back-end interconnection design and logic optimization, can solve the front-end wiring blockage caused by FSPDN, improve performance by 44%, and increase power efficiency by 30%.
