Samsung will launch SF3 and SF4X processes in June this year
In a vigorous effort to ascend to new heights in its foundry business and offer robust competition to TSMC, Samsung is preparing to unveil its SF3 and SF4X processes. As per the official announcement, these technologies will be introduced at the VLSI Technology and Circuits Symposium, slated to take place in Kyoto, Japan, from June 11 to 16, 2023.
Reports by Wccftech suggest that Samsung could officially launch the SF3 and SF4X processes this coming June. Speculations have been rife in recent times that AMD may partner with Samsung on a 4nm process, and a contract has allegedly already been signed between the two. This agreement would see a portion of AMD’s 4nm chip orders shifts from TSMC, requiring a redesign of the codenamed Phoenix Ryzen 7040 series to accommodate the process requirements of Samsung. However, precise details of this collaboration remain scarce, with rumors that Samsung will divulge more specifics next month.
The SF3 (3GAP) is Samsung’s second-generation 3nm process technology, set to utilize the “Second Generation Multi Bridge-Channel Field Effect Transistor (MBCFET)”, making further optimizations over the existing SF3E. Interestingly, Samsung has not compared SF3 with the current 3nm GAA, choosing instead the SF4 (4LPP, 4nm Low Power Process), with the former enhancing performance by 22% under the same power and transistor count, reducing power consumption by 34% at the same frequency and complexity, and shrinking the logic area by 21%. This suggests that the difference between SF3 and the 3nm GAA may not be significant.
SF4X represents Samsung’s inaugural process specifically developed for HPC applications. Unlike SF4 (4LPP), which caters to low-power design in mobile and laptop chips, SF4X can achieve higher frequencies and efficiency, supporting the elevated voltage required for superior performance. This signifies Samsung’s fourth-generation 4nm process. In comparison to SF4, the SF4X improves performance by 10% under the same power and transistor count and reduces power consumption by 23% at the same frequency and complexity.
