Intel unveils Agilex 7 with R-Tile design: First FPGA chip supporting PCIe 5.0 and CXL

Intel has announced the launch of the Agilex 7 FPGA, an innovative contribution featuring an R-Tile design. This marks a first, providing customers with an FPGA chip supporting both PCIe 5.0 and CXL, while also being the only FPGA that backs these interfaces and has hardware intellectual property.

“Customers are demanding cutting-edge technology that offers the scalability and customization needed to not only efficiently manage current workloads, but also pivot capabilities and functions as their needs evolve. Our Agilex products offer the programmable innovation with the speed, power and capabilities our customers need while providing flexibility and resilience for the future. For example, customers are leveraging R-Tile, with PCIe Gen 5 and CXL, to accelerate software and data analytics, cutting the processing time from hours to minutes.” – Shannon Poulin, Intel corporate vice president and general manager of the Programmable Solutions Group

With the Agilex 7 and the R-Tile design, customers can seamlessly integrate the FPGA with products like Intel’s fourth-generation Xeon scalable processors. The Agilex 7’s configurable and scalable architecture allows customers to swiftly deploy custom technology as per specific requirements, reduce overall design costs, and accelerate the development process and execution speed, thereby attaining optimal data center performance.

According to Intel, the Agilex 7, incorporating an R-Tile design, holds a technological superiority over other FPGA products. The PCIe 5.0 promises a twofold bandwidth increase, and the bandwidth per CXL port quadruples its predecessors. When paired with Intel’s fourth-generation Xeon scalable processors and CXL, the use of Efficient Page Placement via Transparent Page Placement (TPP) can enhance Linux performance by 18% and increase the High-Performance Conjugate Gradient (HPCG) benchmark test scores by 28%.