PCIe 6.0 specification enters the final draft stage
PCI-SIG started PCIe 6.0 related work in June 2019. After two years and four months, PCIe 6.0 has reached version 0.9, which is equivalent to the final draft stage. PCI-SIG members are conducting an internal review of the technology to ensure its intellectual property and patents. Unless there is a major problem, no functional modification is allowed. This means that relevant companies can start adopting PCIe 6.0 in their products to ensure that the products comply with the draft specification. It is understood that version 1.0 will be announced at the end of this year or early next year.
PCIe 6.0 will increase the data transfer rate from 32 GT/s of PCIe 5.0 and 16 GT/s of PCIe 4.0 to 64 GT/s per pin, and the theoretical data transfer speed of PCIe 6.0 × 16 channels in one direction will reach 128 GB/s. In order to increase the data transmission rate and bandwidth, the new interface uses four-level pulse amplitude modulation (PAM4) signaling, which is also used in high-end network technologies like InfiniBand and GDDR6X memory. In addition, PCIe 6.0 also uses low-latency forward error correction (FEC) to ensure high-efficiency operation.
Products that support the PCIe 6.0 specification will not be launched so quickly, and the supported platform products are expected to be launched at the end of 2023 or sometime in 2024.
