More info about new generation of EPYC processors revealed
The design of AMD’s Zen 4 architecture EPYC processors is fundamentally established, with only the base setup and edge computing market-oriented Siena due for launch at some point in the latter half of this year. Following this, we will usher in next year’s Zen 5 architecture products. Indeed, AMD’s product roadmap has long delineated the fifth-generation EPYC processor as the Turin family, which, like its predecessor, will have multiple derivative products.
A user released pertinent information about the fifth-generation EPYC processors on his Weibo account. The Zen 5’s CCD, akin to the current Zen 4, possesses eight cores and a 32MB L3 cache. However, enhancements to the front end and CCX architecture will occur, along with a slight upgrade in the L1 cache. It will be produced using Taiwan Semiconductor Manufacturing Company’s 4nm process, and this kind of CCD will be used in the cores of Truin, Granite Ridge, and Fire Range. Compared to the existing Zen 4’s CCD, it is more compact, hence enabling AMD to accommodate more CCDs on the current SP5 interface CPU PCB.
Turin is the code name for the base version of the fifth-generation EPYC processor. It can house up to 16 CCDs, a third more than Genoa, the current Zen 4 architecture’s 12 CCDs, with a maximum of 128 cores, 256 threads, and a total of 512MB L3 cache.
Conversely, Turin-X is naturally stacked with 64MB of 3D V-Cache on Zen 5’s CCD, with a maximum of 16 CCDs, 128 cores, 256 threads. However, the L3 cache capacity has tripled, boasting an impressive 1536MB of L3 cache.
As for Zen 5c, its individual CCD core is 16, with a 32MB L3 cache. The corresponding EPYC processor has a maximum of 12 CCDs, a maximum of 192 cores, 384 threads, and the largest L3 cache capacity of 384MB. It naturally competes with Intel’s forthcoming pure E-Core architecture, Sierra Forest, which, however, only has 144 cores. Both are set to be released around the first half of 2024.
