Kioxia and Western Digital will demonstrate 300+ layers of 3D NAND flash memory
The 2023 VLSI Technology and Circuits Symposium will take place in Kyoto, Japan, from June 11th to 16th, 2023, where Kioxia and Western Digital will showcase their latest innovations to support future high-capacity, high-performance 3D NAND storage devices.
As reported by eeNewsEurope, Kioxia, and Western Digital are pursuing the realization of 1Tb 3D TLC NAND flash memory with eight planes, over 210 active layers, and an interface rate of 3.2 GT/s. This is strikingly similar to the 218-layer 3D NAND flash memory launched in March of this year, with a density of 17Gb/mm², only transitioning from four to eight planes, which to some extent increases the complexity of storage control, raises development and manufacturing costs, and prolongs product development time. It is claimed that its program throughput is 205 MB/s, with a read latency of 40μs.
New papers reveal that Kioxia has achieved a 3.2 GT/s interface rate by reducing the X-direction data query area of the 1Tb 3D TLC NAND flash memory by 41%, resulting in faster data transfer speeds between the memory and host. However, this new design may lead to circuit congestion, and Kioxia mitigates this by introducing a hybrid row address decoder (X-DEC) to more effectively manage the increased wiring density and reduce latency. Additionally, Kioxia employs a single-pulse dual-select technique, allowing the sensing of two storage units within a single pulse, reducing the total sensing time by 18%.
In collaboration, Kioxia and Western Digital are also developing 300+ layer 3D NAND flash memory, planning to adopt metal-induced lateral crystallization (MILC) technology, enabling developers to create 14-micron-long monocrystalline “pasta-like” silicon (Si) channels within vertical storage holes. In experimental operations, developers also utilized a cutting-edge nickel absorption method to eliminate impurities and defects in silicon materials, thereby improving the performance of the cell array, reducing read noise by at least 40% without sacrificing reliability, and increasing channel conductivity tenfold.
