Intel Sapphire Rapids: 60x Cores, 112.5 MB LLC, 96x UPI, 128x PCIe5/CXL, 512b DDR5
Sapphire Rapids is Intel’s next-generation Xeon processor, using the Golden Cove architecture, manufactured using a 10nm Enhanced SuperFin process, with a TDP of 350W. The new platform also supports PCIe Gen5, CXL 1.1 (Compute Express Link), and eight-channel DDR5 memory, while continuing Intel’s built-in AI acceleration strategy and supporting Intel Advanced Matrix Extensions (AMX). In addition, Intel Sapphire Rapids will also launch an HBM version equipped with 64GB of HBM2E memory.
Recently, according to Intel’s high-resolution chip perspective in the ISSCC 2022, we can clearly see the structure of the Intel Sapphire Rapids processor. As a mature multi-core processor, Sapphire Rapids has a CPU core, integrated northbridge, memory and PCIe interface, and other related I/O parts. There are four XCC chips inside, and each uses five EMIB bridges.
The XCC chip used by Sapphire Rapids contains 15 Golden Cove architecture cores, each core has 2MB of L2 cache, and the processor will have a total of 112.5MB of L3 cache. Although Sapphire Rapids’ four XCC chips have a total of 60 cores, only a maximum of 56 cores will be turned on for yield considerations. Each XCC chip will have a 128-bit (160-bit including ECC) memory controller responsible for two DDR5 channels, making the entire package support a total of eight channels of DDR5 memory.
In addition, each XCC chip has a PCIe 5.0/CXL 1.1 interfaces with a total of 32 lanes, which means that Sapphire Rapids will have 128 PCIe 5.0/CXL 1.1 lanes. In the Accelerator tile, the Intel Data-Streaming Accelerator (DSA), QuickAssist Technology (QAT), and DLBoost 2.0 are included, which are hardware involved in accelerating the construction and training of deep learning neural networks. There is also a module with 24 UPIs for interconnection between sockets.
In addition, each XCC chip has a PCIe 5.0/CXL 1.1 interfaces with a total of 32 lanes, which means that Sapphire Rapids will have 128 PCIe 5.0/CXL 1.1 lanes. In the Accelerator tile, the Intel Data-Streaming Accelerator (DSA), QuickAssist Technology (QAT), and DLBoost 2.0 are included, which are hardware involved in accelerating the construction and training of deep learning neural networks. There is also a module with 24 UPIs for interconnection between sockets.
