IME breaks through the quad-Layer 3D stacking technology
As the research and development of semiconductor process technology become more difficult, it is not easy to break through more advanced processes. Not to mention that Intel has been hovering at the 14nm process node for a long time. It is estimated that it will take a lot of trouble to enter the area below 10nm. Even the leading Taiwan Semiconductor Manufacturing Company (TSMC) has recently reported that the 3nm process has been postponed. As for Samsung, the follower behind TSMC, it does not seem to be particularly smooth.
Since the improvement of process technology is hindered, or it is necessary to change the way to improve the performance of future chips, perhaps 3D stacking technology is an option. According to Tom’s Hardware, researchers at the Institute of Microeletronics (IME) have just achieved a technological breakthrough, achieving a stack of up to four semiconductor layers. Compared with the traditional two-dimensional manufacturing technology, it can save 50% of the cost. This technology may be used in future CPUs and GPUs. Perhaps the real new generation of 3D chip stacking is in sight.
Compared with the front-end Semiconductor Manufacturing Company and AMD’s SRAM stacking technology, this new technology of IME goes one step further. In AMD’s prototype design of the Ryzen9 5900X processor using 3D stacking technology, products based on TSMC’s lossless chip stacking technology have only two layers, the first layer is CCX of Zen 3 architecture, and the second layer is 96MB SRAM cache. IME researchers showed another process, through TSV (Through-Silicon-Vias) successfully bonded four independent silicon layers, allowing communication between different molds.
The benefits of this technology are obvious. It can allow chips to be manufactured on different wafers with components of different processes. In the recent Intel speech, it can be felt that the design of new chips has been developed in this direction.
