GH100 based on the Hopper architecture will have 48MB of L2 cache
At the upcoming GTC 2022, Nvidia is likely to bring a new generation of Hopper architecture GPUs. Previously, Nvidia suffered from ransomware attacks by hacker groups. After the internal system was invaded, more than 1TB of data including drivers, design drawings, and firmware was leaked, including materials involving the Hopper architecture. As Nvidia’s first GPU with a multi-chip module design (MCM), the next-generation GPU will be manufactured using TSMC’s (TSMC) 5nm process and CoWoS advanced packaging, supporting HBM2e and other connectivity features for the data center market.
Twitter user Locuza_ has summarized the details of the GH100 based on the Hopper architecture based on the previously leaked information and circulating information. It is understood that the GH100 will have 48MB of L2 cache, which is an improvement compared to the 40MB of the Ampere architecture GA100 and three times the AMD Instinct MI250 (16MB).
However, compared with the 96MB of the flagship chip AD102 of the Ada (Lovelace) architecture, the L2 cache of the GH100 is half less.
GH100 will be equipped with 8 sets of GPCs, each GPC is equipped with 9 sets of TPCs, and each TPC has two sets of SMs. If the CUDA core ratio of each set of SMs does not change, it means a total of 144 sets of SMs and 18432 CUDA cores. And only 1 of the 8 groups of GPCs has a 3D engine, and the other 7 groups will not be equipped. In addition, there is news that the GH100 still uses a single-chip design, and the GH202 will use the MCM design, which may have two GH100 chips. Although the GH100 is equipped with 144 sets of SMs, it should not be all enabled, and Nvidia is expected to disable 15% to 20% of the SMs.
Nvidia CEO Jensen Huang will give a keynote speech at 8:00 am PST on March 22, during which the Hopper architecture will be disclosed for the first time.
