AMD Shares Second Generation 3D V-Cache Technology: peak bandwidth of up to 2.5 TB/s
Currently, AMD’s Zen 4 architecture desktop processors featuring 3D Vertical Cache (3D V-Cache) technology have been on sale for some time. The Ryzen 7000X3D series processors have increased their L3 cache capacity by 64MB compared to the regular models, making them the best gaming processors today. However, AMD did not share details about the second generation 3D V-Cache in the materials for the Ryzen 7000X3D series processors until recently at ISSCC 2023.
According to Tom’s Hardware, in the first generation of 3D V-Cache, AMD used SRAM chips manufactured with a 7nm process stacked on Zen 3 architecture CCDs also manufactured using the 7nm process. The Zen 4 architecture CCDs use a 5nm process, causing some incompatibility, and requiring AMD to make some modifications.
First, the SRAM chips manufactured with a 7nm process are smaller, with a size reduced from 41mm2 to 36mm2 while maintaining a total of approximately 4.7 billion transistors, resulting in higher density. SRAM chips also lack typical cache control circuits, which helps reduce latency. Additional L3 cache adds a signal delay of 4 clocks, but bandwidth has increased to 2.5TB/s, a 25% increase over the previous generation’s 2TB/s.
SRAM chips are connected to the base chip via two types of through-silicon vias (TSV). Power supply TSVs transmit power between small chips, while signal TSVs transmit data between units. In the first generation of 3D V-Cache, both types of through-silicon vias were in the corresponding L3 cache area of the CCD. However, because the Zen 4 architecture CCDs use a 5nm process, the increased density of the base chip makes the L3 cache area smaller. Even if the new SRAM chips are smaller, they will overlap with the L2 cache.
To solve this problem, AMD moved the power supply TSVs to the L2 cache area, while signal TSVs remain in the L3 cache area. For the base chip, AMD achieved an effective area reduction of 0.68 times in the L3 cache, data path, and control logic, reducing the through-silicon via area in the L3 cache by 50% in optimizing the first generation of 3D V-Cache. This reduces additional circuits in the new interface design.
AMD’s 3D V-Cache technology is based on TSMC’s SoIC technology, a lossless chip-stacking technology that means there are no solder bumps or bonding materials used to connect the two chips, and the through-silicon vias can be matched without any type of adhesive material. The second generation of 3D V-Cache uses the same process for connections, with improvements but no change in the minimum TSV pitch. In addition, the SRAM chip and the processor core remain in the same power domain and cannot be adjusted independently. The voltage cannot exceed 1.15V, so the frequency of the small chips is not too high.
At ISSCC 2023, AMD also displayed many details about the 6nm process IOD used in Ryzen 7000 series and EPYC processors. The EPYC processor with the code name Genoa needs to connect up to 12 CCDs, so the corresponding IOD is huge. In contrast, consumer-grade Ryzen 7000 series processors are limited to two CCDs, which is an unchangeable limitation since the corresponding IOD only has two GMI3 interconnects to connect CCDs, which ultimately limits the number of processor cores.