AMD Instinct MI450 will use new XSwitch interconnect structure to compete with NVLink

AMD revitalised its GPU RDNA/CDNA architecture roadmap last year, confirming that the Instinct MI300 series would offer various specifications, including an APU that encapsulates the Zen 4 architecture, CDNA 3 architecture modules, and HBM memory stacks. The El Capitan supercomputer, set to be deployed by the Lawrence Livermore National Laboratory (LLNL) in the United States by the end of 2023, will utilise the Instinct MI300 APU.

At present, the trajectory of supercomputer development hints towards a blend of CPU and GPU components in a single chip. Nvidia has followed suit with the launch of Grace Hopper, which combines an Arm architecture CPU and a Hopper architecture GPU using NVLink-C2C. According to a leaked internal AMD email reported by Wccftech, AMD is shaping its data centre APU series strategy, propelling the development of next-generation chips to supersede the Instinct MI300 series.

This email unveils three pieces of information regarding the new chip – Weisshorn, Instinct MI450, and XSwitch. It’s postulated that Weisshorn refers to AMD’s internal codename for the Zen 6 architecture EPYC series CPU, “Venice.” XSwitch, on the other hand, appears to be a form of interconnect architecture, likely AMD’s response to Nvidia’s NVLink, set to make its debut in the Instinct MI400 series.

Given the information known thus far, CPUs based on the Zen 6 architecture are anticipated to launch around 2025-2026, with the Instinct MI400 series estimated to follow suit. Similar to the Instinct MI300 series, the MI400 series is likely to offer various specifications, such as different HBM class memory stacks. Furthermore, the chip is expected to employ 3D chip stacking technology, with distinct modules manufactured using different processes, and then combined.