Alphawave announced the new chip uses TSMC N3E process
Alphawave recently announced the launch of the ZeusCORE100 1-112Gbps NRZ / PAM4 Serialiser-Deserialiser that supports many standards including 800G Ethernet, OIF 112G-CEI, PCIe 6.0, and CXL3.0. This is also its first test chip using the N3E process. The chip has now passed all necessary tests and will be shown at TSMC’s OIP forum later.
Tony Pialis, President and Chief Executive Officer of Alphawave said: “Alphawave is proud to be among the first to utilize TSMC’s most advanced 3nm technology. Our partnership continues to bring innovative, high-speed connectivity technology that will power the most advanced data centers, and we are excited to showcase these solutions at the TSMC OIP Forum event.”
If the N3 and N5 processes are compared, the former is expected to bring about 10% to 15% performance improvement, or 25%-30% lower power consumption, while would increase the logic density by a factor of about 1.6. N3E is the second-generation 3nm process of TSMC. Compared with the N5 process, the performance improvement is about 18% or the power consumption is reduced by 34%, and the logic density is increased by about 1.7 times. Compared to N3, N3E is expected to be more widely adopted, with mass production in the mid or third quarter of 2023.
From 2022 to 2025, TSMC will successively launch N3, N3E, N3P, N3X, and other processes, and there will be an optimized N3S process in the future, which can cover the needs of different platforms such as smartphones, the Internet of Things, automotive chips, and HPC.
