Zen 6: AMD’s Game-Changer in Chip Design and Graphics

Last year, there was a leak from an AMD engineer revealing details about the Zen 6 architecture, which is internally codenamed “Morpheus” and is slated for fabrication using the 2nm process. Should AMD decide to continue its collaboration with TSMC, given the semiconductor fabricator’s progress, processors based on the Zen 6 architecture could be expected to arrive by the end of 2025 or the beginning of 2026.

Recently, enthusiasts have indicated a significant shift in AMD’s approach with the Zen 6 architecture, opting for 2.5D interconnect technology over the traditional multi-chip module design. This change is poised to enhance bandwidth between smaller chips and reduce latency. Furthermore, client processors based on the Zen 6 architecture are expected to bypass the RDNA 4 architecture entirely in favor of RDNA 5 for the integrated graphics. This suggests that the Zen 6 Ryzen processors may employ more advanced semiconductor processes, with rumors suggesting the possibility of different modules being fabricated using both 2nm and 3nm processes.

The concept of 2.5D interconnect is not new to us; current chips based on the RDNA 3 architecture, such as the Navi 31/32, showcase this design, consisting of a Graphics Compute Die (GCD) and multiple Cache and I/O Dies (MCDs), utilizing two distinct manufacturing processes. In the Zen 6 Ryzen processors, AMD is likely to continue with a configuration of dual Compute Core Dies (CCDs) paired with a single I/O Die (IOD), which might be enlarged to incorporate additional novel technologies.

There have also been rumors suggesting AMD is not currently planning to stack the IOD on top of the CCDs due to the high manufacturing costs associated with such a design, though it may explore introducing this configuration in the future.