TSMC held a 3nm mass production and factory expansion ceremony in Tainan Science Park, Taiwan, recently, officially announcing the launch of mass production of the 3nm process, which will contribute to TSMC’s revenue in the first half of next year. Fab18 in the park where the event is located is a production base for 5nm and 3nm chips, of which Phases 5 to 9 are responsible for the production of 3nm chips.
Dr. Mark Liu, chairman of TSMC, attended the event and said that there is no problem with the yield rate of the 3nm process, and it is expected to create $1.5 trillion of products within five years. Mark Liu also shared TSMC’s 2nm process plan. Related facilities will be built in Hsinchu and Taichung Science Parks in six phases, and are currently proceeding as planned. It was previously reported that the land acquisition delay of TSMC’s 2nm factory may affect the mass production time of the 2nm process, but from Mark Liu’s speech, it seems that the situation is still under the control of TSMC.
According to previous news, TSMC will get the High-NA EUV lithography machine in 2024. It will only be used for R&D and collaboration in the initial stage and will be adjusted according to its own requirements during the period, and then used in mass production at an appropriate time. Unlike the 3nm process node, the 2nm process node will use Gate-all-around FETs (GAAFET) transistors. It is expected that the N2 process will be ready for risk production by the end of 2024, and will enter mass production by the end of 2025, and customers will receive the first batch of chips in 2026.