TSMC said that the 2nm process will enter mass production by the end of 2025
Recently, TSMC has made a breakthrough in the development of the 3nm process. Last year, Dr. Wei, president of TSMC, said that the N3 process node still uses the structure of FinFET transistors. When launched, it will be the most advanced PPA and transistor technology in the industry, and it will also be another mass-produced and durable process node for TSMC.
After achieving a breakthrough in the 3nm process, TSMC seems to have become more confident in the 2nm process. According to TomsHardware, this week TSMC President Wei confirmed that the N2 process node will use Gate-all-around FETs (GAAFET) transistors as expected, and the manufacturing process still relies on existing extreme ultraviolet (EUV) lithography technology. It is expected that TSMC will be ready for risk production by the end of 2024 and enter mass production by the end of 2025, and customers will be able to receive the first batch of 2nm chips in 2026.
Wei believes that TSMC’s N2 process node is on the right track in research and development, and both transistor structure and process progress have reached expectations.
As transistors get smaller and smaller, TSMC has been slower to adopt new process technologies. In the past, it would enter a new process node about every two years. Now it will take longer. The timetable for the N2 process node has always been uncertain, and TSMC confirmed the development of this process for the first time in 2020. According to past information, construction of a supporting fab will begin in early 2022, the construction framework is expected to be completed in mid-2023, and production equipment will be installed in the second half of 2024.
