TSMC introduced 3nm and 2nm process technology
Recently, TSMC convened a press conference in Japan focusing on the latest advancements in fabrication technology, providing a detailed exposition of the N3E process node’s progression and the performance enhancements it brings. Moreover, TSMC presented the much-anticipated roadmap for their next-generation fabrication process, forecasting that the 2-nanometer process will achieve mass production by 2025.
TSMC’s Deputy General Manager, Dr. Kevin Zhang, elucidated the company’s cutting-edge technology during the conference, expressing that TSMC is undergoing rapid development. In 2022 alone, the company garnered a staggering $5.47 billion in investments, and currently boasts a workforce of 8,558, implying that TSMC is rapidly augmenting its facilities and investing time and resources into the development of next-generation processes.
To emphasize the evolution of prior generations of processes, TSMC showcased the performance enhancements of the 5nm process and each of its derivative products. Beyond N5P, N4, and N4P processes, TSMC shared data from the new N4X node, asserting that its performance has escalated by 17% and chip density has increased by 5% compared to the N6 released three years prior.
TSMC reiterated that 3nm process production had commenced from the onset of 2022, and the updated N3E process, having garnered technical certification, is set to hit the market in the latter half of 2023. Furthermore, the N3P process, as a performance-enhanced version of the 3nm process series, will be put into production in the second half of 2023, bringing about a 5% performance increase, a 5-10% power consumption decrease, and a chip density improvement by 1.04 times compared to N3E. On the other hand, due to technological innovations such as autonomous driving, the auto industry’s demand for cutting-edge logic technology and computational power is continually escalating. TSMC plans to introduce N3AE (Auto Early) based on N3E to support the early development of automotive products, thus accelerating their market introduction.
Discussing the eagerly anticipated 2-nanometer process, TSMC stated that the N2’s technology development within the 2nm process is proceeding methodically, with mass production anticipated by 2025. Compared to N3E, TSMC’s 2nm process will adopt nanosheet technology to supplant FinFET transistors, which will enhance performance by 10-15%, reduce power consumption by 25-30%, and augment chip density by 1.15 times.
