TSMC 3nm process will be mass-produced next month
Last month, Samsung held a delivery ceremony for 3nm foundry products using the next-generation GAA (Gate-All-Around) transistor technology at the V1 production line of the Hwaseong factory in Gyeonggi-do. TSMC, as the largest wafer foundry, has also put the production of its 3nm process on the agenda.
According to ctee, after the completion of technology research and development and trial production of TSMC’s 3nm process, the production capacity in the second half of the third quarter of this year will increase significantly. It is expected that it will officially enter the mass production stage in September, which is slightly later than the previously rumored August. It is said that from the trial production stage, the initial yield of the N3 process is better than that of the previous N5 process. Although there have been recent reports that Intel will delay the release of Meteor Lake, TSMC will slow down the expansion plan of 3nm production capacity, but it does not seem to have much impact for the time being.
If the N3 and N5 initial processes are compared, the former is expected to bring a performance improvement of 10% to 15% (same power consumption and complexity), or a reduction of 25%-30% power consumption (same frequency and number of transistors). At the same time, the logic density will be increased by about 1.6 times. It is understood that next year’s N3E will reduce the number of EUV mask layers on the basis of N3, from 25 layers to 21 layers. Although the logic density is 8% lower, it is still 60% higher than the N5 process node.
From 2022 to 2025, TSMC will successively launch N3, N3E, N3P, N3X, and other processes, and there will be an optimized N3S process in the future, which can cover the needs of different platforms such as smartphones, the Internet of Things, automotive chips, and HPC.
