Trillion Transistors by 2030: TSMC’s Packaging Tech Breaks the Limit!

At the IEDM 2023 conference, Taiwan Semiconductor Manufacturing Company (TSMC) unveiled its roadmap for trillion-transistor chip packaging, to be achieved through 3D packaging technology. To realize this ambition, TSMC reaffirmed its ongoing development of the 2nm-level N2 and N2P processes and aims to complete the development of the 1.4nm-level A14 process and 1nm-level A10 process by 2030.

According to TomsHardware, TSMC anticipates that advancements in packaging technologies such as CoWoS, InFO, and SoIC will enable the creation of chips with a trillion transistors around 2030. Additionally, TSMC is endeavoring to construct chips comprising up to 200 billion transistors in a single chip.

In recent years, chip manufacturers have faced challenges in technology and funding, leading to a deceleration in the advancement of cutting-edge semiconductor process technologies. Like its counterparts, TSMC confronts similar challenges. However, as the world’s largest foundry, TSMC is confident that the rollout of 2nm, 1.4nm, and 1nm process nodes will bring further enhancements in performance, power efficiency, and transistor density over the next five to six years.

Currently, Nvidia’s GH100 is among the most complex single-chip designs, housing 80 billion transistors. However, TSMC has indicated that even more intricate single-chip designs with over 100 billion transistors will soon emerge. Manufacturing such large chips becomes increasingly difficult and costly, leading many chip design companies to favor multi-chip designs. AMD’s Instinct MI300X and Intel’s Ponte Vecchio, composed of dozens of smaller chips, are prime examples of this trend.

TSMC predicts that this trend will persist, and in a few years, we will witness multi-chip solutions composed of over a trillion transistors.