SiFive launches new Performance series cores, Intel will use to build RISC-V architecture products
SiFive, a chip design company based on the open-source RISC-V architecture, announced the launch of a new SiFive Performance series of processor cores, including P270 and PP550, the latter being SiFive’s highest performance processor to date. Recently, there is news that Intel intends to spend more than $2 billion to acquire SiFive, and has begun negotiations with SiFive.
The SiFive Performance P550 core uses a 13-stage pipeline, three launches, and out-of-order execution micro-architecture. Each core has its own 32KB first-level instruction cache, 32KB first-level data cache, and second-level cache. A single cluster has up to 4 cores, sharing a 4MB Level 3 cache. The SPEC2006int test score reached 8.65/GHz, supports Linux, and fully supports RISC-V vector extension v1.0rc.
The SiFive Performance P270 core adopts an 8-stage pipeline, dual-launch, sequential execution micro-architecture, fully supports RISC-V Vector Extension v 1.0RC, and combines with SiFive Recode to convert the popular traditional architecture of existing SIMD software into RISC- V Vector assembly code is an ideal substitute for it.
Regardless of whether Intel will eventually acquire SiFive, it seems that it will further advance the RISC-V architecture. According to a report from TomsHardware, Intel will build its own RISC-V development platform “Horse Creek” based on SiFive’s latest Performance P550 core, and will use its next-generation 7nm process manufacturing, which is expected to be seen around 2022 to 2023. It may even be Intel’s first 7nm product.
Prior to the release of Intel’s IDM 2.0 strategy, SiFive has announced that it will cooperate with Intel, and SiFive’s related IP can use Intel’s foundry service (IFS) business. It can be seen that since Pat Gelsinger returned to Intel as the new CEO, Intel is no longer limited to the original x86 processors, it has become more diversified and explored new ideas.
