Samsung reveals 1.4nm process details
Last year, at the “Samsung Foundry Forum 2022”, Samsung unveiled its technological roadmap for the foreseeable future. Notably, the SF1.4 process is anticipated to commence mass production in 2027. Concurrently, there will be an acceleration in the development of 2.5D/3D heterogeneous integration packaging techniques, offering an integrated system solution for foundry services.
According to a report from DigiTimes, Samsung’s Vice President of Foundry, Gitae Jeong, recently divulged in a media interaction that the SF1.4 process technology under development is poised to augment the number of nanosheets per transistor from three to four, potentially heralding significant enhancements in performance and energy efficiency.
Augmenting the number of nanosheets in each transistor bolsters the driving current, thereby enhancing performance. An increased count of nanosheets permits a more copious flow of current through the transistor, amplifying its switching prowess and operational velocity. Furthermore, an enriched cache of nanosheets facilitates superior current regulation, which assuages leakage currents and thereby curtails power consumption. Improved current control also intimates that the transistor generates diminished heat, enhancing power efficiency.
Last June, Samsung pioneered the mass production of the SF3E (3nm GAA) and introduced the novel GAA (Gate-All-Around) transistor technology architecture. Plans for the ensuing year encompass the unveiling of the second-generation 3nm technology dubbed SF3 (3GAP), employing the “Second-Generation Multi-Bridge Channel Field Effect Transistor (MBCFET)”, refining the existing SF3E. Subsequently, the performance-enhanced SF3P (3GAP+) will be launched, tailor-made for the fabrication of high-performance chips. By 2025, Samsung envisages initiating mass production of the SF2 (2nm) process.
TSMC projects the mass production of its N2 (2nm) process by 2025. In parallel, Intel vies for the 2024 mass production of its Intel 20A process. Both these processes will incorporate the GAA transistor design architecture.
