Researchers explain AMD’s 3D vertical cache design in detail
In this year’s Computex 2021 keynote speech, AMD CEO Dr. Lisa Su demonstrated the Zen 3 architecture desktop processor with 3D vertical cache (3D V-Cache) technology. This innovative technology can bring an additional 64MB 7nm SRAM cache for each CCD, which increases the L3 cache capacity of the processor from 32MB to 96MB, which triples the original capacity.
Recently, senior technical researcher Yuzo Fukuzaki published an article clarifying the most reasonable position of AMD’s technology in the processor cache hierarchy. Obviously, through the 3D vertical cache technology, the L3 cache of the processor can be expanded, instead of being used as the so-called “L4 cache”, and the 16-core Ryzen 9 5950X processor has a total of 192MB of L3 cache.
As an SRAM chip, the 3D vertical cache chip is manufactured using a 7nm process with a size of 6×6 m㎡. It is speculated that the 3D vertical cache chip has about 2,300 through-silicon vias (TSV), with a single hole diameter of about 17μm, allowing the bottom layer CCX to be closely connected to the 3D vertical cache chip. Zen 3 architecture processors should consider the possibility of using 3D vertical cache chips at the beginning of the design, which shows that AMD has been developing this technology for many years.
According to AMD’s previous official introduction, the 3D vertical cache technology is based on TSMC’s SoIC technology. As a lossless chip stacking technology, it means that no micro bumps or solder are used to connect two chips, and the two chips are milled into a perfect plane. There is a perfect alignment between the bottom layer CCX and the top layer L3 cache, and the TSV can be matched without any type of adhesive material.
The CCX was flipped (from facing the top to facing the bottom), then 95% of the top silicon was cut off, and the 3D vertical cache chip was mounted on it. The distance between the cache and the core is shortened by 1000 times, reducing heat, power consumption, and latency.
Yuzo Fukuzaki said that in order to deal with the Memory Wall problem, the cache design of the processor is very important. Larger-capacity caches have long become a trend on high-end processors, and 3D vertical cache technology helps to provide processor performance, while also solving the problem of low yield and better controlling costs.
