PCI-SIG published version 0.3 of the PCI Express 7.0 specification
At the 2022 PCI-SIG Developers Conference, the PCI-SIG celebrated its 30th anniversary and announced the next generation PCIe 7.0 specification, planned to be released to its members in 2025. Recently, the PCI-SIG announced the 0.3 version of the PCI Express 7.0 specification. This milestone signals the progress of the PCIe 7.0 specification, indicating that PCI-SIG organization members have reached a consensus on the key features and architecture of the forthcoming technology.
According to a TomsHardware report, the data transfer rate of the PCIe 7.0 specification will double once again, reaching 128 GT/s, significantly higher than PCIe 6.0’s 64 GT/s and PCIe 5.0’s 32 GT/s. A PCIe 7.0 x16 channel can support 512 GB/s, employing four-level pulse amplitude modulation (PAM4) signaling and 1b/1b flit mode encoding and forward error correction (FEC), all of which were functionalities of the previous PCIe 6.0 specification.
Like all other specifications designed by PCI-SIG, each PCI Express specification has five primary nodes.
The 0.3 version: Concept. This draft describes the objectives to be achieved and the methods to attain these goals.
The 0.5 version: First draft. This version must fully address the objectives set in the 0.3 draft, and it includes all architectural aspects and requirements. Moreover, it comprises feedback from all stakeholders, and at this juncture, PCI-SIG members can add functionalities to the specification under development.
The 0.7 version: Complete draft. This version must have a complete set of functional requirements and method definitions, as no new features can be added after this version. In addition, the electrical specification must have been verified using test chips. At this point, PCI-SIG members can propose different implementations of the new interface.
The 0.9 version: Final draft. At this stage, PCI-SIG members are conducting an internal review of the technology to ensure its intellectual property and patents. Meanwhile, no changes to functionality are allowed.
The 1.0 version: Final version. Starting from this version, all changes and enhancements must pass through formal errata documentation and engineering change notices (ECN).
It is understood that the PCIe 7.0 specification requires shorter PCIe traces, thus further reducing the distance between the root device and endpoint devices. Currently, to implement a PCIe 5.0 design, a thicker PCB and higher-quality materials are required, implying an increase in cost. It is still unclear how PCI Express 7.0 considers this aspect.
