Micron is preparing the first batch of GDDR7, Expected to launch in the first half of 2024
Regardless of what product plans Nvidia, AMD or Intel have for next year, Micron has already prepared to bring the next generation of graphic memory. Over the past two years, GDDR7 has been repeatedly mentioned by memory manufacturers, but for a long time, it has not entered the mass production phase. However, it now appears to be truly imminent.
Recently, Micron released its financial report for the third quarter of fiscal year 2023. During the earnings call, Micron President and CEO, Sanjay Mehrotra, confirmed that Micron will choose to launch a new GDDR7 product on the 1ß node next year. However, he did not share the details, such as the specific speed of GDDR7.
In terms of graphics, industry analysts continue to expect the Total Addressable Market (TAM) Compound Annual Growth Rate (CAGR) for graphics to exceed that of the broader market, thanks to the support of customers and data center applications. We anticipate customer inventory to normalize in the third quarter. We plan to launch our next-generation GDDR7 product on our industry-leading 1ß node in the first half of 2024.
Among the products currently on the market, GDDR6 has the highest speed of 20 Gbps (Radeon RX 7900 series), and the GDDR6X provided by Micron for the Nvidia GeForce RTX 40 series can reach up to 22.4 Gbps (RTX 4080). Last year, Samsung indicated that it plans to launch a GDDR7 product with a speed of 36 Gbps, but did not mention a specific timetable. If the memory bus width is calculated as 384 bits, the 36 Gbps GDDR7 can provide a maximum theoretical memory bandwidth of 1.7 TB/s for the graphics card, which is about 70% higher than the current flagship product RTX 4090.
The existing GDDR6 uses the NRZ/PAM2 signal encoding mechanism, with a starting speed of 14 Gbps, while the GDDR6X developed by Nvidia and Micron together uses the PAM4 signal encoding mechanism. NRZ/PAM2 provides 1 bit of data transfer per cycle, PAM4 provides 2 bits of data transfer per cycle, and PAM3 provides 3 bits of data transfer every two cycles.
