Jim Keller shared the RISC-V architecture Ascalaon chip, and make predictions about AMD Zen 5 performance
Jim Keller, a legendary chip architect who has held positions at Intel, AMD, Apple, and Tesla, has been involved in the development of AMD’s K7/K8/Zen architecture series, x86-64 instruction set, and HyperTransport bus, as well as Apple’s A4 to A7 chip development. During his tenure at Tesla, he oversaw the autonomous driving chip project. After concluding his advisory work at Intel, Keller joined AI chip startup Tenstorrent as President, CTO, and board member, and later assumed the role of CEO this year.
As reported by TomsHardware, Jim Keller recently shared the performance of the Ascalaon chip based on the RISC-V architecture in a keynote address, comparing its core with other competitors and asserting that the Ascalaon CPU will offer market-leading integer performance per watt. Intriguingly, the comparison included the Zen 5 architecture core.
In the predicted SPEC CPU 2017 INT Rate benchmark test for measuring integer performance, Tenstorrent anticipates scores of 7.03 and 8.14 for Ascalon 1.9 SPEC2K17INT/GHz and Ascalon 2.2 SPEC2K17INT/GHz, respectively, surpassing Intel’s Sapphire Rapids (7.45), NVIDIA’s Grace (7.44), and AMD’s Zen 4 (6.80). However, it falls short of Zen 5 (8.84), signifying that Zen 5 will be 30% faster in integer workloads than the current Zen 4.
Naturally, Tenstorrent’s performance expectation has a significant drawback: it is not based on actual or even simulated benchmark test results. Although Tenstorrent’s prediction about Zen 5’s score is captivating, the likelihood of complete accuracy is slim. Keller estimates that Zen 5 architecture server processors will have a TDP of less than 250W when operating at frequencies above 4.0 GHz, while Ascalon processors will have a TDP of around 200W when running at approximately 3.80GHz.