Intel may bet on stacked forksheet transistors technology for sub-2nm chips
Intel may refocus on designing transistors for use on 2nm or below semiconductor processes. Recently, a new patent seems to point the way for Intel, namely “stacked forksheet transistors” technology, to keep Moore’s Law going. The patent doesn’t provide much detail, and Intel doesn’t provide PPA (power-performance-area) improvement figures for reference.
Intel said the new transistor design could eventually enable a 3D and vertically stacked CMOS architecture that allows for an increased transistor count compared to current state-of-the-art triple-gate transistors. In the patent, Intel describes the use of nanoribbon transistors and thin films of germanium. The thin films of germanium will act as a dielectric separation wall, repeated in each vertically stacked transistor layer, ultimately depending on how many transistors are stacked on top of each other.
Intel showcased research in 3D logic integration, known at the time as stacked nanosheet transistor technology, at an IEDM event back in 2019. As for the specific data on how related technologies improve transistor density, performance, and energy efficiency, Intel has so far not disclosed.
Imec, a Belgian-based research group, announced in 2019 that it had developed the first standard cell simulation results of related technology, showing that when applied to the 2nm process node, it can significantly improve transistor density over traditional methods. It expects a 10% increase in speed or a 24% increase in energy efficiency at a constant speed, with a 20% reduction in a unit area. In addition, the space occupied by static random access memory (SRAM) will be significantly reduced by 30%.
In fact, Intel and Imec have close and long-standing ties in the field of nanoelectronics, and the latter’s research results are also the basis for Intel’s new patents.
