Intel releases AVX10 instruction set architecture
In 2021, Intel unveiled its inaugural Alder Lake processor, implementing a hybrid architecture. Similar to its predecessor, the Rocket Lake, it supported AVX-256 and AVX-512 instruction sets. However, due to a multitude of considerations, Intel eventually opted to forcibly disable AVX-512. Not only did this decision strip the chip of a unique feature, but it also resulted in the wasteful underutilization of precious chip area, a deficiency that persists in the current Raptor Lake, which does not support AVX-512. In contrast, Intel’s competitor AMD’s Ryzen 7000 series, based on the Zen 4 architecture, fully supports the AVX-512 instruction set, granting it superior performance in certain specific workloads.
Today, Intel has introduced a new Advanced Performance Extension Instruction Set (APX), unveiling the AVX10 instruction set architecture. This will allow both P-Core and E-Core to simultaneously support the AVX-512 instruction set for the first time, remedying the issues encountered with Alder Lake and Raptor Lake. AVX10 boasts all the functionalities of the AVX-512 instruction set and is suited to processors equipped with 256-bit and 512-bit vector registers. The AVX10 instruction set architecture does not support the current generation of processors, instead being designed for future chips intended for consumer and server processors.
As part of the brand-new Advanced Performance Extension Instruction Set, the AVX10 instruction set architecture provides:
- Optional 512-bit FP/int
- 128/256-bit FP/int
- 32 vector registers
- 8 mask registers
- 256/512-bit embedded rounding
- Embedded broadcast
- Scalar/SSE/AVX “promotions”
- Native media addition
- HPC additional functionalities
- Gather/Scatter
- Transcendental support
- Version-based enumeration
- Support for P-Core and E-Core
The AVX10 instruction set architecture is available in two versions: AVX10.1 and AVX10.2. The former solely supports P-Core, while the latter extends support to E-Core, including 256-bit vector length and other new features. Simply put, P-Core can operate using a 512-bit vector length, while E-Core emulates operation at 256-bits, analogous to Arm’s SVE (Scalable Vector Extension) instruction set.
Beginning with Granite Rapids, Intel will support the inaugural version of the AVX10 instruction set architecture, i.e., AVX10.1, marking the commencement of the transition from AVX-512 to AVX10.
