Intel expands its FPGA product portfolio to meet the needs of customized workloads

During the Intel FPGA Technology Day 2023 event, Intel unveiled an expansion of their Agilex FPGA portfolio to cater to custom workload demands, inclusive of artificial intelligence computations, aiming to align with reduced total ownership costs.

Having announced this year an augmentation of their FPGA product investment, they have now introduced 11 out of the initially planned 15 products, concurrently emphasizing the propulsion of their programmable solutions division’s evolution.

Furthermore, Intel announced the open-source Open FPGA Stack (OFS), paired with the inaugural Intel F2000X IPU design and the newly minted Nios V processor’s production-type adapter card, ensuring compatibility with the previously launched Agilex FPGA and Stratix 10 FPGA.

The newly updated Agilex 3 FPGA series is primarily tailored for power and cost-optimized FPGA products, poised to be incorporated into compact monitoring systems, robots, and similar devices. They have introduced the Agilex 3 FPGA B and C series; the former predominantly caters to motherboards and system management, supporting a higher input/output density, while the latter integrates more computational features, mainly for vertical computational integrations.

The Agilex 5 FPGA E series, currently offered in a preliminary trial form, is primarily aimed at embedded edge computing demands, emphasizing low power consumption and high-performance computational traits. Its per-watt efficiency surpasses its competitors by 1.6 times, crafted using the 2nd generation Intel Hyperflex FPGA architecture and Intel’s 7-nanometer process. Collaborations with multiple industrial partners are already underway for device applications, with anticipations of initiating early trials in this year’s fourth quarter and projecting test samples and design software availability by the first quarter of 2024.

Additionally, the Agilex 7 FPGA, furnished with the R-Tile architectural design, now incorporates the CXL 2.0 IP capability. It can accommodate up to double the PCIe 5.0 transfer bandwidth and a whopping four times per-port CXL bandwidth for heightened data transfer volumes. The FPGA’s configuration can be expanded based on specific requirements, catering to bespoke application needs, consequently optimizing overall design expenses and developmental workflow, thereby accelerating execution speeds and achieving optimal data center performance.