Imec announces sub-1nm transistor roadmap, 3D-Stacked CMOS 2.0 plans
Established in 1984, IMEC currently stands as Europe’s leading independent research center, primarily focusing its investigative endeavors on microelectronics, nanotechnology, supplementary design methods, and information communication systems technology (ICT). Recently, IMEC unveiled its sub-1nm process roadmap, sharing pertinent transistor architecture research and development plans.
According to reports from TomsHardware, IMEC’s process roadmap signifies that FinFET transistors will reach their pinnacle at 3nm, transitioning subsequently to the new Gate All Around (GAA), projected for mass production in 2024, followed by FSFET and CFET among others. An “A” represents Angstroms, with 10A equating to 1nm.
As time progresses, migration to smaller process nodes becomes increasingly costly. Traditional single-chip design methods have yielded smaller chip designs, effectively deconstructing the varied functionalities of a chip into several smaller chips, which are then interconnected to operate as a cohesive unit. IMEC’s vision for the CMOS 2.0 paradigm involves disassembling the chip into smaller segments, separating caches and memories into units with distinct transistors, subsequently arranged in a 3D stacking pattern atop other chip functionalities. This method will heavily rely on the backend power distribution network (BPDN), shifting all power supply to the rear of the transistor.
Reconsidering the design process through system technology co-optimization (STCO), modeling the system and target application requirements, then utilizing this knowledge to provide information for chip design decisions. In this process, the chip is dissected into individual units to optimize the performance characteristics required for each unit using different types of transistors, thereby reducing costs. One of its objectives is to separate cache/memory into its own unique 3D stacking design layers, thus decreasing the complexity of chip stacks.
CMOS 2.0 is the pathway to genuine 3D chips. Currently, AMD employs 3D V-Cache technology to stack L3 cache atop computation chips to augment capacity. IMEC envisions the entire cache hierarchy incorporated within its own layer, with L1, L2, and L3 caches vertically stacked above the transistors constituting processing cores. Each cache layer will be constructed using transistors most suited for the task. As the scaling of SRAM has considerably decelerated, it implies that SRAM can potentially utilize older process nodes to reduce costs. Ideally, 3D stacking can also help mitigate latency issues associated with large caches.
