Future of Transistors? Intel, TSMC, & Samsung Duel Over CFET Tech
At last week’s IEEE IEDM conference, Intel, TSMC (Taiwan Semiconductor Manufacturing Company), and Samsung showcased their respective CFET (Complementary FET) transistor strategies. The stacked CFET architecture, intertwining both n-type and p-type MOS devices, is poised to supplant the GAA (Gate-All-Around) technology and emerge as the next-generation transistor design. This innovation is set to double the density of current designs.
Intel was the first wafer foundry to demonstrate a CFET solution, having unveiled an early version as far back as 2020. At this conference, Intel presented several enhancements to one of the simplest circuits in CFET manufacturing – the CMOS inverter. This inverter transmits the same input voltage to the gates of both devices in the stack, producing an output logically opposite to the input, all within a single fin. Intel also increased the number of nanosheets used in the transistors from two to three and reduced the vertical gap from 50nm to 30nm.
The current 5nm process node features a gate pitch of 50nm, utilizing a simple FinFET with single-sided interconnects. Samsung’s CFET proposal, however, boasts a gate pitch of 45/48nm, smaller than Intel’s 60nm. Although the 45nm gate pitch variant in Samsung’s CFET prototype saw a decrease in performance, researchers believe that this can be rectified through optimization of the manufacturing process. Samsung’s achievement lies in its ability to electrically isolate the stacked n and p MOS devices’ source and drain, a critical step achieved using a novel dry etching technique involving wet chemicals, replacing the traditional wet etch process. Unlike Intel’s three nanosheets per transistor, Samsung utilizes a single nanosheet for a pair of transistors.
Like Samsung, TSMC also managed to control the gate pitch at 48nm in their CFET design. Their approach features a novel method for forming a dielectric layer between the top and bottom transistors to maintain the gap. Typically formed from alternating layers of silicon and germanium, TSMC experimented with a germanium-specific etching technique to build an isolation layer between the two transistors before releasing the silicon nanowires.
It is understood that the commercialization of CFET technology on a large scale is still approximately 7 to 10 years away, with much preparatory work remaining before this groundbreaking technology can be fully realized.
