AMD launched the K6-2 processor in 1998, manufactured using a 0.25-micron process, and aimed at Intel’s Pentium II processor. It is the first application of the 3DNow! instruction set, which includes 21 new instructions, making the K6-2 processor the first x86 processor capable of executing floating-point SIMD instructions, providing higher performance for vector processing of floating-point data.
Two years later,
AMD introduced the K6-2+ processor, manufactured on a 0.18-micron process and equipped with a 128KB L2 cache. Although the name seems to be just an extra “+” sign, the micro-architecture is different. The K6-2+ processor is the same as the K6-III+ processor. The difference is that K6-III+ is equipped with a 256KB full-speed L2 cache, and the former has a capacity of 128KB, which is halved.
According to
TomsHardware, recently, some hardware enthusiasts discovered that by moving the position of the capacitor near the processor core, the L2 cache capacity of the K6-2+ processor can be doubled and unlocked into a K6-3+ processor. The results of performance tests show that this method is feasible. This approach is not without risk though, with all L2 cache enabled, the chip seems to become less stable.