With the introduction of the Intel Alder Lake processor, the CPU will soon enter a new round of war. AMD will launch a Zen 3 architecture desktop processor equipped with 3D V-Cache technology early next year, at the same time, a new generation of Zen 4 architecture processors will be released around the end of the year to cope with a series of challenges from Intel’s 12th generation Core series processors.
Earlier this year, a large number of confidential documents involving companies such as Intel and AMD were exposed, some of which were about the Zen 4 architecture. Recently, technical experts have interpreted the details of the cache design of the Zen 4 architecture based on documentation.
If nothing happens, the L1 instruction/data cache of the Zen 4 architecture is still 32KB, with 8 associated channels, but the L2 cache will be doubled on the basis of the Zen 3 architecture, from 512KB to 1MB, however, 8 channels are still associated, and the L3 cache situation is temporarily unclear due to lack of data. In Intel Alder Lake’s Golden Cove architecture and Gracemont architecture cores, the L2 cache corresponds to 1.25MB per core and 2MB per four cores. This means that the fully configured L2 cache of Alder Lake has a total of 14MB. With the Zen 4 architecture equipped with 16 cores, the L2 cache will have 16MB, which will be larger than Alder Lake.
Although Intel and AMD differ in cache design, the cache size is only one of them, and there are other technologies, in particular, the hybrid architecture of Alder Lake will be quite different, but it cannot be denied that L1 and L2 caches play an important role in branch prediction. The Zen 3 architecture uses 3D stacking technology to bring an additional 64MB 7nm SRAM cache to each CCX, which increases the overall game performance of the processor by 15%. In modern processors, the cache system plays an important role in IPC and is also the key to evaluating the architecture.